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GaN-on-SiC vs GaAs at Ka-Band: A Direct Efficiency Comparison

Head-to-head measurement data comparing drain efficiency, OIP3, and thermal floor for GaN-on-SiC and GaAs processes at 26.5 to 40 GHz.

GaN-on-SiC vs GaAs at Ka-Band: A Direct Efficiency Comparison

Ka-band, the frequency range from 26.5 to 40 GHz, is where the comparison between GaN-on-SiC and GaAs is most consequential for current satellite and 5G infrastructure design. Below 20 GHz, GaAs is well-established and the performance gap is smaller. Above 50 GHz, InP begins to dominate and the GaN vs GaAs question recedes. Ka-band is the contested zone.

This article examines the three metrics that most directly determine system design choices at Ka-band: drain efficiency at operating back-off, OIP3 per unit DC power, and the effective thermal floor set by substrate conductivity. The data referenced draws on published characterization results from open literature and our own design analysis for the FA-2400 series. We flag clearly which figures are Falcomm design targets versus general industry-published ranges.

Drain Efficiency at Ka-Band: Physics and Measured Ranges

GaN-on-SiC devices at Ka-band operate with supply voltages typically between 20 and 40V, depending on gate length and device topology. The higher supply voltage compared to GaAs (typically 3-7V at Ka-band) enables operation with a higher output impedance, which makes broadband matching networks more practical and allows more of the device current swing to contribute to RF power output rather than reactive circulating current.

Published drain efficiency data for GaN-on-SiC PA devices in the 28-40 GHz range consistently shows peak efficiency between 35% and 55% at P_sat for mature 100-150 nm gate length processes. At P1dB minus 3 dB, which is a more representative operating point for most commercial applications, efficiency typically falls to 25-42% depending on topology and bias conditions. For Doherty designs with auxiliary PA peaking, efficiency at 6 dB output back-off can reach 30-38%, compared to 15-22% for a conventional class AB GaAs design at the same back-off.

GaAs pHEMT processes at Ka-band typically show peak drain efficiency of 20-32% at P_sat for 100-150 nm gate length devices. At P1dB minus 3 dB back-off, efficiency ranges from 14-24% in published characterization data. The lower supply voltage means the load line voltage swing is a larger fraction of the supply, which limits efficiency at back-off as the device current drops but the supply voltage remains fixed.

The net efficiency advantage of GaN-on-SiC over GaAs at Ka-band in typical commercial designs is 10-18 percentage points at P_sat and 8-16 percentage points at moderate back-off. These are not marginal differences; they are the difference between a system that can be cooled passively and one that cannot.

OIP3: How Process Affects Linearity at a Given Back-Off

Output third-order intercept point (OIP3) is a measure of a device's immunity to intermodulation distortion. In a satellite link carrying multiple carriers or a 5G mmWave sector serving multiple UEs simultaneously, OIP3 determines the interference floor between channels.

The relationship between OIP3 and P_sat for a well-designed PA is typically characterized by the ratio OIP3/P_sat, measured in dB. For class AB PAs, this ratio typically falls in the range of 8-12 dB above P_sat. GaN and GaAs devices at Ka-band show similar OIP3/P_sat ratios for a given topology. The advantage of GaN in a system context comes from P_sat itself: a GaN device can achieve a given P_sat at lower relative device dissipation, so for the same OIP3 target, the GaN device is operating at a lower fraction of its saturation point, which means it has more linearity margin.

Stated differently: if your system requires OIP3 of 45 dBm, and a GaAs device achieves this at P_sat = 33 dBm with drain efficiency of 22% at that operating point, you dissipate considerable power. A GaN device that achieves P_sat = 36 dBm at 45% efficiency meets the same OIP3 target at a lower fraction of its saturation, with significantly lower dissipation per unit of OIP3 delivered. The OIP3 specification by itself does not tell you this story; the OIP3 per unit DC power ratio does.

Thermal Floor: Why Substrate Conductivity Matters at Millimeter Wave

The thermal conductivity of the substrate below the device channel determines how rapidly heat generated at the junction spreads laterally before reaching the package flange. At Ka-band, device geometries are small and power density is high. A Ka-band GaN device with 4 mm of total gate periphery dissipating 1W has a power density of 250 mW/mm, which is high enough that lateral heat spreading within the substrate significantly affects junction temperature even at modest total power levels.

SiC substrate thermal conductivity of approximately 400 W/m-K means heat from the channel spreads rapidly across the die before reaching the flange, distributing the thermal load more evenly. For a 2x2 mm die footprint, the temperature difference between the hottest point (directly above the gate periphery) and the average flange temperature is roughly 8-15 degrees C in a well-designed SiC-substrate device at typical power levels. For a comparable GaAs die (thermal conductivity approximately 45 W/m-K), the same calculation yields 50-90 degrees C hotspot-to-flange differential, a 5-6x larger gradient.

This gradient has a direct consequence for output power derating. If the maximum junction temperature is 200 degrees C (a typical limit for GaN-on-SiC), and the GaN device has a hotspot-to-flange delta of 12 degrees C, then at a 75 degrees C flange temperature the available thermal headroom at the junction is 113 degrees C. At 2W dissipation and a junction-to-flange resistance of approximately 6 degrees C/W, the junction is at 87 degrees C, well inside the limit. The GaAs device in the same thermal scenario would have a junction-to-flange resistance of 35-50 degrees C/W, placing the junction at 145-175 degrees C, pushing near or into the derating region.

Where GaAs Still Makes Sense at Ka-Band

We are not arguing that GaAs is the wrong choice for Ka-band categorically. For low-noise amplifier (LNA) designs, GaAs and InP remain the preferred substrate because noise figure performance is the binding spec and thermal dissipation in the LNA is low. For receive-path variable-gain amplifiers and switch ICs, GaAs process maturity and cost are compelling. For small-volume, cost-sensitive applications where peak efficiency is less critical than proven supply chain and assembly yields, GaAs is a reasonable choice.

The GaN advantage is specific to transmit-path PAs in applications where output power is high enough that dissipation matters, and where device density is high enough that thermal management is a design constraint rather than a straightforward heatsink selection. LEO gateway uplinks, 5G mmWave macro-cell base station AAUs, and high-density phased array radar front-ends meet those criteria. Low-power handheld terminals and receive-path components typically do not.

Falcomm's Design Targets for Ka-Band

For the FA-2400 series, our design targets at Ka-band are based on our analysis of the efficiency and thermal data described above, applied to the specific constraint set of phased array terminals and base stations. We target drain efficiency above 45% at P1dB minus 3 dB across the 27.5-30 GHz uplink allocation, with junction-to-flange thermal resistance below 4 degrees C/W at module level.

These are design targets under validation, not production measurements. They represent what our device architecture and process choices aim to achieve, grounded in the published GaN-on-SiC performance ranges described in this article. We will publish full characterization data when the validation campaign is complete. Until then, these numbers should be treated as design goals that reflect our analysis of where GaN-on-SiC can push the Ka-band efficiency boundary in a production-capable PA module format.