Junction-to-case thermal resistance (Theta_jc) appears on most RF PA datasheets as a single number, often measured under carefully controlled conditions that do not reflect what the device sees in a deployed phased array. Understanding what that number means, where it underestimates real-world behavior, and how it limits the achievable element density in your array is foundational to any thermal architecture decision.
This article works through the physics of PA thermal resistance, the measurement conditions that commonly produce optimistic datasheet values, and the translation from element-level Theta_jc to array-level density limits. We also discuss where GaN-on-SiC substrate conductivity changes the thermal equation relative to GaAs, and what design targets we are pursuing for the FA-2400 series based on those considerations.
The Thermal Resistance Chain
The total thermal path from a PA device junction to the ambient environment passes through several resistive layers in series: junction to case (Theta_jc), case to board or mounting surface (Theta_cb), board or module to heatsink (Theta_bh), and heatsink to ambient (Theta_ha). The specification that PA datasheets provide, Theta_jc, is only the first link in that chain.
For a PA mounted in a QFN package on a PCB substrate, the effective junction-to-ambient resistance in a real assembly is typically 3-5x the datasheet Theta_jc value when the full chain is accounted for. The thermal interface material between the module and the heat spreader typically adds 0.4-1.2 degrees C/W depending on compound type, applied pressure, and surface flatness. The PCB thermal via array adds another 0.5-2 degrees C/W depending on via diameter, via fill, and copper plating thickness.
For a PA with datasheet Theta_jc of 3 degrees C/W and total chain resistance of 12 degrees C/W operating at 2W dissipation per element, the junction temperature rise above ambient is 24 degrees C. At 4W dissipation per element, it is 48 degrees C above ambient. If ambient is 45 degrees C in a deployed outdoor unit, junction temperature in the second case reaches 93 degrees C. That is within the rated range for most GaN devices, but it is high enough to begin affecting gain and phase stability, and it compresses the reliability margin.
What Datasheets Typically Measure and What They Miss
Theta_jc is typically measured using a calibrated cold plate with a flat, polished contact surface and a known thermal compound applied at a controlled pressure and thickness. The measurement follows JEDEC JESD51 or a vendor-specific procedure. The result is a junction-to-case resistance for that specific package under those specific interface conditions.
Three things are commonly absent from the published number. First: sensitivity to substrate surface finish. A cold plate in a lab has a surface roughness Ra of 0.1-0.5 micrometers. A machined aluminum housing in production may have Ra of 1.6-3.2 micrometers. Surface roughness increases the TIM contact resistance by increasing the average gap that TIM must fill. Second: variation across the mounting footprint. The datasheet value is an average; the temperature distribution under the package is non-uniform because heat generated at the device channel flows to the edges of the flange before it contacts the heatsink. Third: sensitivity to torque. Flanged packages depend on bolt torque to achieve proper TIM compression. Undertorqued flanges show substantially higher effective Theta_cb than the specified value.
None of these omissions represent poor engineering on the part of the device manufacturer. They reflect the practical limitation that a meaningful Theta_jc value under all possible installation conditions would require publishing a matrix of values rather than a single number. The hardware team's job is to recognize where the datasheet measurement condition departs from their installation condition and to add an appropriate margin.
Array Density and the Thermal Crosstalk Problem
In a phased array, element spacing is set by the wavelength and the acceptable grating lobe level. At Ku-band (14 GHz), lambda/2 spacing is approximately 10.7 mm. At Ka-band (28 GHz), it is 5.4 mm. At those pitches, the thermal spreading footprints of adjacent elements overlap in the PCB substrate and the underlying heat spreader.
The overlap creates thermal crosstalk: heat from element N raises the local substrate temperature under element N+1, increasing its junction temperature above what its own dissipation alone would produce. In a 64-element array, the center elements see contributions from multiple neighbors. The temperature differential between a center element and an edge element can reach 15-30 degrees C under continuous wave loading, depending on the substrate thermal conductivity and the heat spreader design.
That temperature gradient has two consequences. First, the gain and phase of the hotter center elements drift relative to the cooler edge elements. In a beamforming array, this means the calibrated beam pattern degrades over the first several minutes after power-on as the array reaches thermal equilibrium. Second, the sustained output power must be derated to keep the hottest element below the maximum junction temperature, which means the center elements cannot operate at the same power level as the edge elements without violating thermal limits.
Reducing per-element dissipation directly reduces both the magnitude of the temperature gradient and the derating requirement. This is where PA drain efficiency at operating back-off is the variable that controls array density: every percentage point of efficiency improvement at the operating point translates directly into reduced dissipation per element and reduced thermal crosstalk in the array.
GaN-on-SiC Substrate Conductivity and Its Practical Effect
Silicon carbide substrate thermal conductivity is approximately 370-400 W/m-K, compared to gallium arsenide at 45-46 W/m-K and silicon at 148 W/m-K. This difference directly affects how heat spreads from the active channel region through the substrate to the package flange.
For a GaN-on-SiC device with a 0.15 mm thick SiC substrate between the channel and the package flange, the spreading resistance within the substrate contributes roughly 0.3-0.8 degrees C/W per 100 micrometers of substrate thickness, depending on the active area geometry. For a comparable GaAs device, the same geometry would contribute 2.5-4 degrees C/W per 100 micrometers. The SiC substrate reduces the junction-to-flange component of Theta_jc significantly.
This matters most when the package geometry limits heat spreading area. In a compact QFN or flip-chip package where the flange area is comparable to the die area, lateral spreading through the substrate is the primary heat distribution mechanism. A more conductive substrate produces a more uniform temperature distribution across the package flange, which in turn means the TIM at the flange-to-heatsink interface operates with a more uniform temperature gradient and achieves closer to its datasheet thermal resistance.
Translating These Constraints to Design Decisions
For a hardware team designing a phased array front-end, the thermal resistance specification affects three decisions: element spacing and array density, heat spreader thickness and material, and PA derating factor at the system operating point.
The element spacing decision must account for thermal crosstalk, not just RF performance. Calculating the element-to-element thermal coupling requires a thermal simulation of the full array structure with realistic heat sources, not just the single-element datasheet Theta_jc. That simulation should use the realistic total thermal chain resistance, including the TIM adder and the PCB via resistance, not the optimistic datasheet value.
The heat spreader thickness decision trades between thermal spreading effectiveness and mechanical constraints. A thicker copper spreader reduces center-to-edge temperature gradient but adds weight and increases the mechanical resonant frequency of the assembly. For an airborne or satellite-mounted array, weight is a binding constraint that cannot be traded away freely.
For the FA-2400 series, our design target is a Theta_jc that supports element spacing at or near lambda/2 at Ku-band in a 64-element array without requiring active liquid cooling, assuming a reasonable copper heat spreader and a production-grade TIM. That is a design goal based on our simulation work and our device architecture choices. We are validating it against real measurements as our characterization progresses, and we report design goals as goals, not as specifications, until that validation is complete.